1. Technical Field
The present invention relates to a method of inspecting mask pattern and a mask pattern inspection apparatus, and in particular to a method and an apparatus useful for inspecting pattern defect on a mask which is configured by a multi-layered-film mask substrate which reflects EUV (Extreme Ultra Violet) light, and a finely-patterned material layer formed thereon using a material which absorbs the EUV light.
2. Related Art
Semiconductor devices (semiconductor integrated circuit devices) are manufactured on a mass scale by repetitively using a photolithographic process, in which a mask, or a plate having a circuit pattern, is illuminated by light, so as to project the circuit pattern through a reduction optics onto a semiconductor substrate (referred to as “wafer”, hereinafter).
Keeping pace with recent advances in shrinkage of the semiconductor devices, investigations have been made on increase in resolution by further shortening wavelength of photo-lithography. In place of conventionally developed ArF lithography which makes use of argon fluoride (ArF) excimer laser light at 193 nm, EUVL (Extreme Ultra Violet Lithography) at a far shorter wavelength of 13.5 nm has been under development.
Since transmissive masks are of no use in this wavelength range due to absorbance of light by the constitutive materials, so that multi-layered-film reflective substrates, which make use of reflection (Bragg reflection) on multi-layered films typically composed of molybdenum (Mo) and silicon (Si), are used as mask blanks for EUVL.
Multi-layered film reflection may be understood as reflection making use of a sort of interference. The mask for EUVL is configured by a multi-layered-film blank which is composed of a quartz glass substrate or low-thermal-expansion glass substrate, and a multi-layered film typically composed of Mo and Si formed thereon, and an absorber pattern formed on the blank.
In the process of transfer of the absorber pattern onto a semiconductor wafer, any defect in the absorber pattern is causative of defect in the semiconductor integrated circuit, so that the absorber pattern needs defect inspection before the mask is supplied. Die-to-die comparison method, illustrated in FIG. 14, is a conventionally known method of inspecting mask defect, in which two chips (chips A, A′) 70, 71 having the same pattern are respectively observed in a scanning mode using a sensor having a plurality of pixels, the obtained chip images are compared, and any difference therebetween is detected using an appropriate defect detection algorithm (see Japanese Published patent application A-H10-282008, Japanese Laid-open patent publication 2004-212221, 2004-61289 and 2004-77390, for example).
In view of efficient capture of chip images, it is preferable to scan, en bloc, over a plurality of dies which are aligned in sequence in the longitudinal direction of a stripe-form area (stripe) 72. For this purpose, a method generally adopted is such as sequentially capturing the images, storing the captured images into a memory, and comparing the images in the memory concomitantly with the storage operation, or upon completion of the storage operation for a single stripe.
Another known method is die-to-database comparison method, in which a design data used for designing the geometry of the absorber pattern is read, the read data is subjected to an appropriate filtering operation, and then compared with a chip image to thereby detect any difference therebetween.
The filtering operation is aimed at degrading the design data while considering degradation in an actually-obtainable inspection image ascribable to manufacturing processes, resolution characteristics of the inspection optics, characteristics of the sensor and so forth, so as to match it to the actually-obtainable inspection image.
As a method of inspecting defect of the filmy mask pattern, there has been known another method of precisely detecting defect, by appropriately correcting a drawing pattern data to thereby generate a pattern inspection data, so as to avoid difference between the pattern inspection data and an image data obtainable by a pattern defect inspection apparatus, and then by comparing the pattern inspection data and the image data (see Japanese Laid-open patent publication NO. 2007-11169).
FIG. 12A illustrates an exemplary EUVL mask M1, under development by the present inventors, as viewed from the patterned surface. The mask M1 has a device pattern area MDE which represents a semiconductor integrated circuit pattern located at the center thereof, and alignment mark areas MA1, MA2, MA3, MA4 which typically contain mask alignment marks and wafer alignment marks located in the peripheral area.
FIG. 12B is a drawing illustrating an exemplary section of the EUVL mask M1, taken at the device pattern area MDE. It is seen that a multi-layered film 52 described in the above is provided on a substrate 51 which is composed of quartz glass, low-thermal-expansion material or the like, and a capping layer 53 is provided thereon. Further thereon, an absorber pattern 55 is provided, while placing a buffer layer 54 in between. On the other hand, on the back surface of the substrate 51, there is provided a metal film 56 coated thereon, for the convenience of electrostatic chucking of the mask.
FIG. 13 is a drawing illustrating a system used for reduction projection of a pattern on the EUVL mask M1, making use of an EUV projection exposure apparatus. EUV light having a center wavelength of 13.5 nm, emitted from a light source 61, propagates through an illumination optics 62 configured by multi-layered-film reflection mirrors, and illuminates the patterned surface of the EUVL mask M1 pattern.
Reflected light on the patterned surface then propagates through a reduction projection optics 63 composed of multi-layered-film reflection mirrors, and projects the mask pattern onto a semiconductor wafer 64. The semiconductor wafer 64 is placed on a stage 65, so as to allow a large number of patterns to be transferred onto desired areas on the semiconductor wafer 64, by repeating movement of the stage 65 and the pattern transfer.
The present inventors, however, found out a problem in the above-described technique of inspecting pattern defect in the EUVL mask used for the EUV projection exposure apparatus.
In the EUV lithographic apparatus, scattered stray light (flare) ascribable to surface roughness of the mirrors composing the projection optics tends to increase, so that even portions of the pattern, expected to be darkened, may adversely be affected by the flare in the process of demagnifying transfer of the pattern on the EUVL mask M1 onto the semiconductor wafer.
As a consequence, the line width of a projected image may vary if the periphery of the pattern is bright. Since the total amount of scattered light increases inversely proportional to the square of wavelength, so that the amount of flare in EUVL, making use of light at a wavelength shorter by one order of magnitude than that in the conventional photo-lithography, increases by two orders of magnitude or more.
Moreover, influences of the flare may vary depending on to what degree the bright portion occupies the area within a micrometer- or millimeter-order range around a target pattern.
Accordingly, on the EUVL mask, even the same geometrical patterns on the design basis including the adjacent patterns need be applied with different flare correction patterns, depending on positions of the chips containing such patterns. In optical proximity correction (OPC) adopted in the conventional photo-lithography, it has been good enough if only the same correction pattern is adopted to the same geometrical patterns including the adjacent patterns.
In contrast, EUVL is different from the conventional OPC in that even the same geometrical patterns including the adjacent patterns need different flare correction, depending on the pattern density in the range as small as the chip size.
As a consequence, as illustrated in FIGS. 15A and 15B, an absorber pattern 73 contained in chip A and an absorber pattern 72 contained in chip A′ have different dimensions on the mask, even if they have the same geometrical patterns on the design basis. For this reason, the conventional die-to-die comparison method suffers from a problem of inaccurate inspection.
On the other hand, the die-to-database method may successfully avoid a problem of degraded inspection accuracy ascribable to the different dimension as described in the above. The filtering operation described in the above, however, needs a huge volume of calculation, making it difficult to achieve satisfactory levels of accuracy and rapidness in the inspection at the same time.